(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a shallow trench-deep trench isolation region.
(2) Description of Prior Art
Bipolar devices offer increased performance when compared to counterparts such as complimentary metal oxide semiconductor (CMOS) devices, therefore designs featuring a combination of fast, bipolar devices, with CMOS devices, are now being implemented. The implementation of bipolar-CMOS (BiCMOS), technology does however require additional features not needed for CMOS only devices. For example due to the shallow depth of CMOS features, only shallow trench regions are needed for isolation of specific CMOS regions, however the deeper features and regions used with the bipolar technology require a greater depth for adequate isolation. Junction isolation can be used for devices needing the deeper isolation regions, however the capacitance generated with this type of isolation adversely influences performance, therefore deep trench isolation has emerged as the logical choice for isolation for bipolar technologies, with a shallow trench-deep trench combination used for BiCMOS devices.
The definition of, and the filling of, deep trench features can result in unwanted topographies. The topography created by deep trench regions, either extending above or below the top surface of a semiconductor substrate, can allow formation of conductive rails on surfaces exposed on the raised or recessed trenches, conceivably resulting in leakage or shorts between devices intended to be isolated via the deep trench procedure. The unwanted rails formed from deposition of a conductive material such as polysilicon, on the raised or recessed deep trench sides, remain after anisotropic dry etching procedures are performed to define a device feature in the conductive material. Therefore to successfully employ deep trench, or a combination of shallow and deep trench technology, the presence of a smooth top surface topography, at the conclusion of the isolation definition procedure is imperative.
This invention will describe a process sequence used to fabricate a shallow trench-deep trench isolation region in which the desired smooth top surface topography is realized prior to formation of the CMOS and Bipolar elements, thus reducing the risk of rails and leakage between features of these devices. This is accomplished via a series of polishing, deposition, and definition procedures, designed to result in the desired smooth top topography of the isolation region. Prior art such as Wu, in U.S. Pat. No. 6,214,696B1, Akram, in U.S. Pat. No. 5,895,253, Lin et al, in U.S. Pat. No. 6,232,043B1, Jang, in U.S. Pat. No. 6,194,287B1, Sune, in U.S. Pat. No. 6,255,184B1, and Liu, in U.S. Pat. No. 6,110,794, describe methods of forming isolation regions in semiconductor substrates, however none of the above prior art described the novel combination of process sequences used in the present invention, designed to present a smooth top surface topography for devices formed and isolated using shallow trench-deep trench regions.